| 职位类别： | 其他 | 工作性质： | 全职 | 招聘部门： | |||
| 工作地区： | 江苏苏州市 | 招聘人数： | 3人 | 截止日期： | 2010-12-01 | ||
| 薪资待遇： | 面议 | ||||||
| 所处商圈： | 周边地铁： |
|
|||||
| 工作经验： | 十年以上 | 学 历： | 本科 | 性 别： | 不限 |
| 年 龄： | 语言要求： | 流利 ; | 现居住地： | ||
| 虚拟面试： | 无 | 是否拒收未参与面试简历： 否 | |||
| 职位描述： | Job description:In this position, you will be responsible for mixed-signal chip's logic design and verification, including block level specification, micro architecture design, RTL coding and verification, synthesis and power and static timing analysis. You will lead other digital designers to successfully complete projects on schedule.Requirements: 1.Excellent Verilog coding and RTL design skills2.Proficient with Verilog simulator, Synopsys power and timing analysis tools3.Hands on experience in low power design preferred4.Knowledgeable in all aspects of digital design5.Successfully gone through several complete product development cycles6.Capable of defining chip architecture and design specification7.PhD with 3+years industrial experience or MSEE with 6+ years industrial experience in IC design8.Demonstrate leadership and work well with cross-functional teams9.Dedicated, hard working and good team player10.Posses excellent interpersonal as well as good communication skills |
| 任职条件： |
